CONFUSED!!! WinXP vs. WinXP 64?!!

[MrPolite]

I'm looking at Microsoft's website... there is Windows XP and "Windows XP 64-bit Edition". What is this? is the the Home and Professional edition?

[kalicki]

XP64 is NOT what you want...

XP has the normal Home and Pro...

[MrPolite]

eeh then what's XP64?!!

[filburt1]

Originally posted by MrPolite
eeh then what's XP64?!!

It runs only on 64-bit processors such as the Itanium and the 'Hammer series from AMD. All consumer processors right now are 32-bit.

[MrPolite]

sounds like very yummy, I hope win.net has a 32 bit edition...
They're eventually gunno make 64 bit processors for consumer use too, right?

[JungleMan]

AMD is coming out with one early next year. Intel just doesn't care about consumer 64 bit...keep ramping up them megahertz

[Zaei]

Will I be able to get a 64 bit Win2k?

Z.

[JungleMan]

I doubt it...

BTW, AMD's new chip is going to run 32 bit apps too.

[MrPolite]

so what exactly is the difference between a 32 bit and a 64 bit processor? does that mean that the 64bit one can process twice information at a time?

[Zaei]

The processor will work on 64bit values, instead of 32. When an n-bit processor does a memory retrieval, it gets n bits, regardless of the actual requested size. Once it has its n bits, it trims it down to however many were actually requested, or requests more if more was requested. So, on a 32 bit processor, 32 bit values are the fastest, while 64 bit values require 2 memory retrivals, etc. 64 bit processors only need one.

Z.

[siyan]

Intels Itanium is pure 64 bit. Thus, requiring a translator for 32 bit code, it runs 32 bit apps like arse. But it is quite a killer in pure 64 bit stuff.

AMD's Hammer is X86-64 based, a hybrid 32/64 bit CPU that runs 32 bit stuff every bit (no pun intended) as well as current leading consumer CPUs, as well as 64 bit stuff very well.

-C

[siyan]

Uhh...also I'm guessing that 64 bit CPUs can take a more varied set of instructions.

Like, when you look at disassembly code, every CPU instruction is in a 4 letter word (4 x 8 bits = 32 bits)

So a 64 bit CPU coudl take 8 bit words?

I'm sure that there is a better explaination of the benefits somewhere

-C

[Emo]

Maybe this will clear out some questions...

http://www.tweakmax.com/html/64bit/64b-3.cfm

-Emo

[Zaei]

Originally posted by siyan
Uhh...also I'm guessing that 64 bit CPUs can take a more varied set of instructions.

Like, when you look at disassembly code, every CPU instruction is in a 4 letter word (4 x 8 bits = 32 bits)

So a 64 bit CPU coudl take 8 bit words?

I'm sure that there is a better explaination of the benefits somewhere

-C

The assembly opcodes you see in a disassembly are just mnemonics for their machine code counterparts. There COULD be an opcode "do_something_cool_or_else! 10", which would simply compile down to a few bytes pf machine code. In other words, the mnemonics you see could be anything, as long as the assembler knows that x should be y, and compiles accordingly.

In fact, the Intel 80x86 instruction set is usually 3 letter mnemonics =).

Z.

[JungleMan]

Originally posted by siyan
AMD's Hammer is X86-64 based, a hybrid 32/64 bit CPU that runs 32 bit stuff every bit (no pun intended) as well as current leading consumer CPUs, as well as 64 bit stuff very well.

As a matter of fact, I stumbled across some leaked benchmarks for the 800Mhz Clawhammer and it supposedly is beating the 1.6 Pentium 4 in Quake 3 (and a version not compiled for 64 bit either). It's expected to start at 2Ghz, imagine what it should do to the competition at even higher speeds. The SOI technology is also exciting, perhaps we can get some nice 50% overclocks. 3Ghz hammer, mmmm

[Gandalf_Grey_]

Originally posted by JungleMan


As a matter of fact, I stumbled across some leaked benchmarks for the 800Mhz Clawhammer and it supposedly is beating the 1.6 Pentium 4 in Quake 3 (and a version not compiled for 64 bit either). It's expected to start at 2Ghz, imagine what it should do to the competition at even higher speeds. The SOI technology is also exciting, perhaps we can get some nice 50% overclocks. 3Ghz hammer, mmmm

those were leaked? wow, i didn't think AMD would be that careless. Although i guess that it would be kinda hard to keep the overzealous techies who designed the chip shut up . I already have about $100 in my hammer fund

Justin: how much do you think they will be worth when they first come out?

[plenderj]

Something I might mention, a 64bit processor is not just twice as complicated as a 32bit processor.

It'd require, by my reckoning, and by my cpu design college courses, about 2^32 more components and circuit paths inside the cpu itself.

[JungleMan]

Originally posted by Gandalf_Grey_


those were leaked? wow, i didn't think AMD would be that careless. Although i guess that it would be kinda hard to keep the overzealous techies who designed the chip shut up . I already have about $100 in my hammer fund

Justin: how much do you think they will be worth when they first come out?

I've heard they will be more expensive than most chips upon release, but not sure of exact numbers...

[Gimlin]

what kind of Mobo will support it?

[siyan]

Originally posted by Gimlin
what kind of Mobo will support it?

A new kind

AMD already has Hammer compatable chipsets obviously..if they've done testing.

I'm pretty sure they're using a new form factor and all. So dont' worry, new chipset from AMD, then VIA will make a better one, then everyone rolls out the mobos

-C

[Pc_Madness]

I read somewhere about Intel making a Processor capable of handling to apps at once, instead of the just 1.

Anyone know anything about this?

[siyan]

Probably some extension of hyper threading...

[Warmaster199]

Originally posted by Pc_Madness
I read somewhere about Intel making a Processor capable of handling to apps at once, instead of the just 1.

Anyone know anything about this?

Just get LINUX, BeOS, UNIX, or Windows(Oops, did I say that?) and then you can run 500 apps at once on one processor

Looks to me like Intel STILL think's it's customers are idiots if they are making hype about multi-app processors... Sorry to "burst your bubble"

[Pc_Madness]

Originally posted by Warmaster199


Just get LINUX, BeOS, UNIX, or Windows(Oops, did I say that?) and then you can run 500 apps at once on one processor

Looks to me like Intel STILL think's it's customers are idiots if they are making hype about multi-app processors... Sorry to "burst your bubble"

Well all Processors can handle one Application at a time... so they just change quickly inbetween apps if theres more than one.

With the new sort, two programs can run at once... meaning its twice as fast.

[filburt1]

Originally posted by JungleMan
BTW, AMD's new chip is going to run 32 bit apps too.

At good speeds though?

[JungleMan]

Originally posted by filburt1


At good speeds though?

Supposedly with more efficiency than even the Athlon XPs.

[Warmaster199]

A system with multiple chips on a single die(That's what intel is going to make, right? 2 CPUs on a single chip)...

IBM is going to(Or do they have it already???) make the first Petops(Quadrillion operations / sec) computer. They plan to do this with 100's of Cubes of 4 boards, each with 32 chips, each with 4 cores... The system can figure out if boards have failed and then they can be "hot swapped" without affecting the system.
Looks like "Big Blue" beat them to it, eh?

As for the Athlon: Isn't the 1.6GHz Athlon XP capable of outperforming a 2.0GHz Pentium IV? I'd like to see more on this new AMD chip.

[plenderj]

Multithreading at the OS level is nothing to do with their hyperthreading etc. technology at the chip level.

For example, windows uses time division multiplexing, as more than likely do all operating systems, to divvy out cpu time to threads. So then that app's instructions are sent one by one to the CPU.

At the CPU side of things, once an instruction has entered the 'pipe' (ie. its already half way executed), then another intstruction can be put into the 'pipe' too.
This way multiple things get done at the same time quicker.

[plenderj]

Originally posted by Warmaster199
A system with multiple chips on a single die(That's what intel is going to make, right? 2 CPUs on a single chip)...

Well the first Pentium (P5) was actually basically 486 processors stuck together, and it was capable of executing two instructions at the same time.

Oh yeah another thing I might mention, the Itanium processor, instead of dealing with a 64bit instruction at a time, it can execute two 32bit instructions, or 4 16bit instructions at a time.

[Warmaster199]

The P5 took the Execution units of two 486's and stuck them together - They didn't make 2 seperate cores. How many instructions can a P5 fetch per clock cycle? I believe it's only 1. HOWEVER, what the P5 CAN do is fetch on one cycle, and then execute the instruction and then fetch again on the next, while one unit is executing. This is called pipelining...

The IBM chip that I was talking about earlier is capable of making 4 memory access(fetch cycles) per clock cycle - One for each of the whole cores. Each core fetches for itself, while with the P5, the control unit fetches for the execution units one at a time.

This is why a 486DX-4 @ 100MHz can tie a P5 @ 75MHz. But how so? The P5 is like the 486, but two execution units. It can still noly access one instruction per cycle...

[Warmaster199]

The P5 took the Execution units of two 486's and stuck them together - They didn't make 2 seperate cores. How many instructions can a P5 fetch per clock cycle? I believe it's only 1. HOWEVER, what the P5 CAN do is fetch on one cycle, and then execute the instruction and then fetch again on the next, while one unit is executing. This is called pipelining...

The IBM chip that I was talking about earlier is capable of making 4 memory access(fetch cycles) per clock cycle - One for each of the whole cores. Each core fetches for itself, while with the P5, the control unit fetches for the execution units one at a time.

This is why a 486DX-4 @ 100MHz can tie a P5 @ 75MHz. But how so? The P5 is like the 486, but two execution units. It can still noly access one instruction per cycle...